1. Field of the Invention
The present invention relates to a DLL (Delay Locked Loop) circuit and a semiconductor device including the same, and more particularly relates to a DLL circuit that can be locked in a short time and a semiconductor device including the same. The present invention also relates to a data processing system including the semiconductor device.
2. Description of Related Art
In recent years, a synchronous memory that operates synchronously with a clock has been widely used as a main memory of a personal computer or the like. Particularly, a DDR (Double Data Rate) synchronous memory requires input/output data to be accurately synchronized with an external clock. Therefore, it is essential to provide a DLL circuit to generate an internal clock synchronous with an external clock. Japanese Patent Application Laid-open No. 2007-243735 discloses an example of such a DLL circuit.
The DLL circuit has a function of adjusting a position of a rising edge of an internal clock, and a function of adjusting a position of a falling edge of the internal clock, thereby matching a phase of the external clock with that of the internal clock. The rising edge of the internal clock is regulated by a rise clock generated within the DLL circuit, and the falling edge of the internal clock is regulated by a fall clock generated within the DLL circuit.
When the rising edge of the internal clock is advanced relative to the rising edge of the external clock, an active edge of the rise clock is delayed by one pitch. On the other hand, when the rising edge of the internal clock is delayed relative to the rising edge of the external clock, the active edge of the rise clock is advanced by one pitch. Similarly, when the falling edge of the internal clock is advanced relative to the falling edge of the external clock, an active edge of the fall clock is delayed by one pitch. On the other hand, when the falling edge of the internal clock is delayed relative to the falling edge of the external clock, the active edge of the fall clock is advanced by one pitch.
However, when an adjustment direction of the rise clock and an adjustment direction of the fall clock are the same, that is, when the active edges of both clocks are delayed by one pitch, or when the active edges of both clocks are advanced by one pitch, a duty does not change as compared with that before the adjustment, although phases are adjusted to a direction to which the internal clock and the external clock come closer. Therefore, the number of steps necessary to adjust thereafter the duty of the internal clock increases. As a result, the time required to lock the DLL circuit becomes long.